Design Complexity

Chip padring design is inherently complex and labor intensive, because the padring is where electrical, timing, physical, and logical views of the design all come together. A padring design for wire bonding can often require 20 to 30 percent of the total IC design effort. Flip chip, because of its high I/O count and potential for very high bus speeds, greatly increases padring design complexity. Pad ring design effort for flip chip can exceed 50 percent of the total chip design effort.

To obtain very high speed performance, designers must precisely specify "on-chip" wire lengths. In source-synchronous designs, such as a double data rate memory bus, the designer must position logic associated with an I/O pin physically close to that I/O pin. Commercial electronic design automation (EDA) tools move this logic into the core, rather than placing it close to the pin. Also, commercial EDA tools are not well suited to specify precise wire lengths. Consequently, engineers must draw wires and place and route "affinity" logic by hand. Similarly, designers must manually pre-route balanced buses, and insert repeaters on long nets.

Another complexity of flip chip design is coping with soft errors. Foundry design rules do not allow solder bumps to be placed over SRAM locations, to avoid soft errors caused by alpha particle emissions from the solder alloy. It becomes impractical to adhere to this rule in a networking chip, where the SRAM can occupy over 50% of the die area. Parity bits have to be added to the SRAM cells, and error recovery, such as retransmit requests, must be handled by the system software.

Package Design

There are many factors to consider in selecting the correct flip chip package. Cost comes first. Flip chip package costs range from $20 to over $125, depending on the die size and bump pitch. Paradoxically, a larger die may mean a cheaper combined package and die cost.A lower package cost results, because a die with a larger bump pitch can go into a significantly cheaper package than the same chip designed as a smaller die with a tighter bump pitch. Therefore, the design team must consider the cost of the die and package combination, not just each cost in isolation.

Another package design challenge is to correctly determine the final bump locations as part of the initial design. A design team can make a rough analysis based on the package vendor’s design rules. However, if there are more than two rows of active pin rows (pins whose signals go into the core), the routing pitch and bump location pitch must ensure that all leads (wires) internal to the package can get past the bump contact locations. High-speed bus design requirements complicate this issue, because tight timing skew specifications require that all of leads internal to the package to every pin on a bus must be ofthe same length. Thus the chip design team must work iteratively with the package design team to find signal and power/ground pin locations that meet the design constraints of both teams.

Correctly selecting the initial bump locations is crucial, because, once chosen, they are considered fixed reference points for the balance of the design. Changing bump locations on the die requires a new package design, with substantial delays. This accuracy in initial planning for flip chip bump locations is a new and stringent design requirement. Wire bond pads are more forgiving of location changes, because wire lengths and directions can accomodate some pad changes; solder bumps are fixed. The fastest way to assure that the initial die bump locations are acceptable, and not likely to change, is to make a top-level placement and route, and have it approved by the package vendor.

Engineering Change Orders

Since most chip bond rings and solder bump locations for flip chip package designs are built by hand, changes are time-consuming, requiring months to implement. For example, the SPARC-5 flip chip design pinout was published for over a year before the board designers discovered that thermal considerations required relocating the cache memory. It was moved to the opposite side of the chip, rotating the memory bus 180 degrees. The chip redesign to move the pins took over three months.

ReShape is a physical design outsourcing company serving customers doing customer-owned tooling (COT) design. ReShape is developing unique technology that automates the process of designing complex, high-performance, integrated circuits. By taking advantage of automation, ReShape can build chips of high quality (small and fast), faster and with less risk than conventional human-intensive services.

ReShape has developed an automated methodology that addresses the problems encountered when laying out a padring. It becomes particularly valuable when designing flip chips. Key is an automated IC layout design flow enabling the flip chip design to be completed in days, compared with the months required by the traditional manual design process. The fast turnaround of this highly automated capability solves the three flip chip design challenges described above.

At the core of ReShape’s capability is its Design Flow Automation Engine. The automation engine takes netlist and floorplan files, and outputs chip layouts in GDSII. All user directives to the physical design process are captured in chip specification files. The automation engine’s GDSII output is specific to the targeted process and semiconductor foundry.

The automation engine is a combination of commercial and proprietary EDA tools. ReShape selects the best available commercial tools for algorithmically intensive tasks such as placement, routing, timing verification, extraction, LVS, DRC, and formal verification. Proprietary tools are developed in-house when no commercial tool solves a problem. These proprietary tools typically perform methodology-intensive tasks, such as padring or flip chip bump construction.

At the heart of the automation engine are three knowledge bases. The first is the design flow knowledge base. This is captured know-how on how to build complex chips using hierarchical design techniques. The second is the tool know-how knowledge base. The results that a design gets out of a tool are a function of how expert the designer is at tweaking the literally thousands of knobs available on a power tool. The third is the design-specific knowledge acquired from each design iteration. This enables ReShape to use information from past experiments to improve the design.

Design Complexity Reduction

ReShape is focused on completely automating padring design so that designers can spend their time solving the difficult problems that make each padring unique, and less on implementation details. Complexity is reduced through high-level specification and precise timing control of logic associated with pins.

ReShape’s framework supports a high-level language that enables rapid pad location specification. The locations are specified as a regular bump pattern that can be replicated, and tailored to a specific design. The padring is broken down into zones in which the I/Os, bumps/bond pads, and edge logic are laid out in a regular pattern. A layout editor and perl environment is provided which then allows the regular patterns to be tailored to handle the unique cases. All this is done in conjunction with package routing and selection and chip floorplanning so that the system will work together. Finally, bump patterns can be saved and modified for future chips in the same family.

Locating logic near pads enables precise timing control from pin-to-core, and core-to-pin. Critical timing logic assigned to an I/O driver is referred to ‘edge’ or ‘affinity’ logic. Edge logic is very difficult to control in conventional place and route flows, because the place and route algorithms pull this logic into the core. The ReShape framework allows edge logic cells to be laid out at specific locations within the bump patterns.

Iterative Package Design

A fast iterative design flow enables designers to rapidly converge on a solder bump layout that meets the chip designer’s and package designer’s goals. The designer specifies new bump locations in a high-level language. The automation can return results in minutes, in contrast to today’s manual methods that return results in months. This level of automation provides unprecedented speed to generate prototypes quickly to see if a pinout is feasible and determine what package is required. With the automated ReShape flow, the IC design team can do "what if" analyses between the tradeoffs of die size and bump pitch, and therefore the routing capacity between bump locations on the package. These analyses can greatly affect the cost of a package die solution. The design team can also explore possible "keep-out" areas over RAM locations.

Quick ECO Implementation

ReShape's flip chip automated design flow enables quick, predictable, repeatable changes. For example, a ReShape chip with over 3,000 pins allowed the designer to re-specify bump patterns and pin-out definitions, and have a new balance bus network automatically implemented in less than 6 minutes.