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Nailing ICs Together
George A. Riley, PhD
FlipChips Dot Com
INTRODUCTION
A promising technique for high-density 3-D stacked ICs (SiC) is to directly interconnect stacked die with copper "nails" instead of the wire bonds.
First-generation stacked die in chip-scale packages depend upon multi-level wire bonding for interconnections. (Figure 1) While IC packaging density is increased, signal speed is limited by the inductance and capacitance of the long wire bonds.
Also, wire bonds require relatively large pads, and cannot provide minimum length direct chip to chip functional block connections within the die. Most present applications are for stacked memory die with peripheral bonding pads.
Figure 1. Stacked die with wire bond interconnections in a chip-scale package.
(ChipPAC photo)
Continuing research by IMEC has developed through-wafer direct die-to-die copper area-array interconnections. [1] Protruding ends of through-wafer copper vias ("nails") placed anywhere on the die are directly connected to an adjacent die by thermo-compression bonding.
Advantages of nailed stacked die include:
Higher speed Lower power consumption Smaller die size Shortest path length Functional block interconnections Highest interconnect density Stacking different devices and technologies.
Figure 2 diagrams copper nail connection of two thinned die to a third die. [2] The 5 micron diameter vias allow a connection density of up to 10,000 vertical connections per square millimeter of surface area. The die could be logic, memory, detectors, and MEMS devices -- all be connected in one stack.
Figure 2. Interconnection diagram. (Courtesy IMEC)
In Figure 2, all three of the ICs (gray areas) show several layers of copper metallization (red) applied in standard back-end-of-line (BEOL) processing. The BEOL areas on the surface of each die are shown as magenta.
The copper nails are the vertical red lines linking to the BEOL metallization of each thinned die. An oxide layer (light-blue) insulates the nail from the innards of the die. The die are bonded into a stack by adhesive layers (green).
PROCESS FLOW
After the wafer completes FEOL processing in the wafer foundry, sprayed photoresist is patterned for the interconnection vias. [3] The 5 micron diameter high aspect ratio vias are etched 25 microns into the silicon from the top side. [4] The vias are copper-filled during the first BEOL metallization step. The wafers then continue to normal BEOL processing.
Figures 3a through 3f illustrate the key thinning, etching, and bonding steps after leaving the wafer line for post-BEOL processing of the filled vias. [5]
Figure 3a. The first post-processing step after leaving wafer fabrication is attaching a carrier wafer so that the device wafer can be handled and thinned. Controlling the glue layer thickness and planarity are critical to minimizing total thickness variation across the wafer. The glue must hold the wafer firmly to the carrier, but be easily removable without residues. [6]
Figure 3b. After attaching the carrier, the wafer is first thinned by grinding to remove about 675μm of silicon. This brings the lower surface close to the bottom of the vias. Grinding must be carefully controlled to maintain planarity and not affect chip performance.
Figure 3c. Thinning is completed by chemical-mechanical planarization (CMP) to planarize the bottom of the wafer and to expose and planarize the copper nails.
Figure 3d. An etching step removes silicon, lowering the bottom surface about one micron and exposing that length of the nails. The following SEM photo shows a single copper nail protruding above the wafer surface after silicon etching: [2]
Figure 3e. Sawing the wafer and carrier provides individual single die. For stacking, a die is aligned and connected by simultaneous thermocompression bonding of all its copper nails to the copper landing pads of the next die or wafer. The best reported results were obtained with a citric acid pre-bond surface treatment and a nitrogen blanket to limit oxidation during bonding. [7]
Figure 3f. The final step is to remove the carrier. Another die can then be nailed to previously-formed landing pads on top of this one.
RESULTS
Testing of nailed assemblies showed normal die shear strengths and connection resistances. Daisy-chain test assemblies showed up to 10,000 good vias. Figure 5 is a portion of one daisy-chain assembly after the die silicon was completely removed, revealing the vertical shafts of the copper nails, and the rectangular copper daisy-chain connecting pads, which had once been on the surface of the die. [2]
Figure 5. Portion of a daisy-chain structure after removing the silicon to reveal the vertical copper nails and connecting pads.
CONCLUSIONS
IMEC has clearly demonstrated and documented the feasibility of copper nails for direct chip stacking. Several challenges to commercialization are being addressed. Aggressive thinning of die is limited by possible internal damage. Thermal considerations become critical as stack power density increases, especially if heterogeneous die differ in their thermal expansion coefficients.
Reliability and yield remain to be established, and they will largely determine costs and commercial applications. For volume production, the equipment, skills, process flow and costs must ultimately be within the reach of commercial foundries.
Still, our industry mantra remains "Smaller, faster, lower cost" – and IMEC's "nailed die" have already achieved two of the three.
REFERENCES
1. P. De Moor, W. Ruythooren, P. Sousan, B. Swinnen, C. Van Der Hoof, E. Beyne, "Recent Advances in 3D Integrations at IMEC," MRS Fall Meeting, November 27 – December 1 2006, Boston.
2. W. Ruythooren, S. Stoukatch, K. Lambrinou, P. De Moor, B. Swinnen, "Direct Cu-Cu Thermo-Compression Bonding for 3-D Stacked IC Integration," IMAPS 2006, October 8 – 12, San Diego.
3. N. Pham, M. Vanden Bulche, P. De Moor, "Spray Coating of Photo Resist for Realizing Through-Wafer Interconnects," EPTC 2006, December 6 – 8, Singapore.
4. D. Tezcan, K. De Munck, N. Pham, O. Luhn, A. Aarts, P. De Moor, K. Baert, C. Van Hoof, "Development of Vertical and Tapered Via Etch for 3D Through Wafer Interconnect Technology, " EPTC 2006, December 6 – 8, Singapore.
5. K. De Munck, J. Vaes, L. Bogaerts, P. De Moor, C. Van Hoof, B. Swinnen, "Grinding and Mixed Silicon Copper CMP of Stacked Patterned Wafers for 3D Integration" MRS Fall Meeting, November 27 – December 1 2006, Boston.
6. K. De Munck, L. Bogaerts, D. Tezcan, P. De Moor, B. Swinnen, K. Baert, C. Van Hoof, "Wafer Level Temporary Bonding/Debonding for Thin Wafer Handling Applications," IMAPS International Conference and Exhibition on Device Packaging, March 2006, Scottsdale.
7. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbondell, K. De Munck, B. Eyckens, S. Stoukatch, D. Tezcan, Z. Tökei, J. Vaes, J. Van Aelst, E. Beyne, "3-D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-silicon vias," IEDM 2006, December 11 – 13 2006, San Francisco
FOR MORE INFORMATION
The primary source is the referenced IMEC papers, which contain far more information than cited here.
For further details, contact IMEC
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