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C4NP Preliminary Test Data Dr. George Riley
FlipChips Dot Com
Suss MicroTec presented a report of preliminary C4NP manufacturing and reliability test results at the IMAPS Device Packaging Conference on March 21. Manufacturing data included bump height distribution and bump shear. The results show that the C4NP process is very robust.
Reliability data included temperature cycling, temperature-humidity testing, and high temperature storage testing, all under a variety of conditions. No failures were found for up to 2,000 cycles of -40°C to 115°C temperature cycling, or for 2,000 hours of 150°C storage, or for 264 hours of biased temperature/humidity testing.
Table 1 gived the distribution of bump heights for two lead-free solder materials. The precise control over solder volume which is inherent in the injection molding process gave excellent uniformity. SAC bumps had a wafer mean bump height of 101.3μm, with a wafer sigma of 2.7μm and a chip sigma of 1.7μm. SnCu bumps had a mean height of 79.9μm, with a wafer sigma of 2.8μm and a chip sigma of 2.3μm.
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Wafer Size, (mm) |
200 |
200 |
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Chip Size (mm) |
14.7 by 14.7 |
14.7 by 14.7 |
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Bumps per chip |
2,452 |
2,452 |
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Bumps per wafer |
284,432 |
284,432 |
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Bump pattern |
Array |
Array |
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Bump pitch (mils) |
4 on 9 |
4 on 9 |
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Wafer quantity |
3 |
3 |
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Pb-free alloy |
Sn3.8Ag0.7Cu |
Sn0.7Cu |
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Bump heights (μm) |
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Wafer mean |
101.3 |
79.9 |
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Wafer sigma |
2.7 |
2.8 |
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Chip sigma |
1.7 |
2.3 |
Table 1. Bump height distribution
These tests included six 200mm wafers, three bumped with SAC and three with SnCu alloys. Each 14.7mm die had 2,452 four mil bumps on nine mil pitch, for a total of 284,432 bumps per wafer.
Table 2 compares bump shear data for the injection-molded C4 bumps with plated bumps of the same two materials. The measured shear strengths of the C4NP bumps were not significantly different from those of plated bumps, both when initially deposited, and after 8 and 13 reflows.
Table 2. Bump Shear Data
Table 3 shows humidity testing, temperature cycling, and high temperature storage results after JEDEC conditioning. No failures occurred for the stated test times.
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Test Description |
Results |
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JL4 + HAST 110°C/85%RH/3.7V/264hours |
0/48 fail |
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JL4 + DTC -40°C/115°C/2000 cycles |
0/42 fail |
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JL4 + ATC 0/125°C/3000 cycles |
0/41 fail |
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JL4 + HTS 150°C/2000hours |
0/43 fail
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Table 3. Reliability test results after JEDEC level 4 conditioning.
Table 4 shows biased temperature/humidity and temperature cycling for two different die sizes. Again, no failures occurred.
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Test Description |
Results |
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JL3 + HAST 130°C/85%RH/no Bias/96hours |
0/23 fail |
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JL3 + DTC -55°C/125°C/1000 cycles |
0/39 fail |
Table 4A: Reliability test data, 14.7mm die test data
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Test Description |
Results |
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JL4 + HAST 130°C/85%RH/3.7V/96hours |
0/15 fail |
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JL4 + DTC -40°C/125°C/1000 cycles |
0/72 fail |
Table 4B Reliability test data, 18.5 mm die.
Summary: Preliminary results to date verify that there are no inherent failure mechanisms attributable to the C4NP process. Qualification testing is scheduled for completion later this year.
FOR MORE INFORMATION
Klaus Ruhmer et al., "C4NP - First Manufacturing & Reliability Data for High End Flip Chip Solder Bumping" IMAPS Device Packaging Conference, Scottsdale, Arizona, March, 2006.
IBM / SUSS MicroTec C4NP Links
Tutorial 55, on this site, gives more details about the C4NP process.
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