Four years have passed since Tutorial 3 described the basics of gold stud bump flip chip. Two years have passed since Tutorial 27 identified further gold stud bump applications. Since then, continuing improvements in gold stud bumping equipment, capabilities, materials, and costs have made gold stud bump the technology of choice for a growing variety of flip chip assembly applications. This update summarizes some of the more recent gold stud bump developments and applications.

New stud bumping equipments from several manufacturers have nearly doubled the bump placement rate from the 12 bumps per second given in Tutorial 3. The newer equipments also accommodate larger wafers, up to 300 mm diameter. Automated wafer-handling equipment has been introduced, to load and unload wafers from the bumping equipment. These improvements have greatly reduced bumping time, and increased throughput. Since stud bumping is a serial process, increased throughput translates directly to higher volume production and lower bumping costs.

Recent cost-of-ownership modeling has shown gold stub bumping costs below $40 per wafer for up to 250,000 bumps per wafer. (Ref 1 ) Figure 1 models the price per bumped wafer versus the total number of bumps per wafer for four common bumping technologies. The upper three bands in the figure are for wafer-based bumping processes, where price is independent of the number of bumps. The red and blue curves show bumping costs for first and second generation stud bumping equipment. First generation stud bumping costs are below $40 per wafer for wafers with fewer than 150,000 total bumps. Second generation stud bumping equipment extends that $40 limit to nearly 300,000 bumps per wafer.

In addition to higher bumping speed, the new equipments give increased flexibility for bump shaping. Bumps can now be formed with shapes optimized for specific assembly techniques. (Ref 2) Figure 2 shows a bump shaped specifically for thermocompression or thermosonic flip chip assembly. The blunt point focuses the force towards forming an intermetallic bond at the pad surface.

Figure 3 shows a bump with a matte finish for conductive adhesive assembly. The conductive adhesive clings more readily to the roughened surface before curing.

Figure 4 shows a flat-top bump for dispersive assembly with non-conductive adhesive. The flat top squeezes out the non-conductive adhesive between the bump and bond pad, allowing a gold to gold mechanical contact.

As gold ball wire bonders have moved towards finer and finer pitch (pad spacing), gold stud bumpers, which share the bonder technology, have followed. Stud bump pitches of 50 microns or less are possible with newest equipment. (Ref 3) These permit higher density interconnection than solder bumping, which is typically limited to pitches in excess of 150 microns. The finer stud bump pitch makes possible applications such as focal plane imaging arrays.

The earlier tutorials assumed stud bumps were formed from gold-palladium (Au-Pd) wire. This wire, harder than pure gold, is commonly used to obtain more consistent wire breakage after forming the bump, resulting in shorter, more uniform wire tails. A recent paper reports that 99.99% (4N) pure gold wire offers several advantages over the 'traditional' gold-palladium wire. (ref 4) The softer gold wire shows wire tails and bump co-planarity as good as Au-Pd wire. The softer wire provides stronger bonds than Au-Pd wire. These bonds are formed with lower bonding forces than for Au-Pd wire. Lower bonding forces permit stud bumps to be placed over active areas of the die without the risk of damaging underlying devices, a limitation of conventional Au-Pd stud bumps. Lower bumping forces are also preferred for bumping thinned wafers and brittle materials.

The continuing search for lead-free solder substitutes has opened new opportunities for gold stud bump. The lower processing temperature and higher electrical and thermal conductivities of gold stud bump flip chip offer advantages over both lead-based solder and alternative lead-free solders.

For example, gold stud bumps with gold-to-gold interconnect have demonstrated advantages over both leaded and lead-free solders in packaging high power light-emitting diodes (LEDs). (Ref 5). The higher electrical conductivity of gold bumps compared to solder lets them withstand higher current densities. The higher thermal conductivity of gold compared to solder alloys better carries heat away from the device. The greater strength and higher operating temperature limits of a gold to gold system increase device reliability. The lower processing temperatures for gold bumping and thermosonic gold to gold interconnect allows the continued used of present polymeric packaging materials; the higher reflow temperatures of lead-free solder substitutes would require replacing these materials. The flux-free gold to gold system requires no aggressive cleaning, and does not risk residue deposits on the optical surfaces.

As both the cost and the minimum pitch of gold stud bumping continues to shrink, it is becoming a practical lower-cost alternative to indium bumping and hybridization for high bump count focal plane arrays. (Ref 6) Gold stud bump connections assembled with conductive adhesive require very low perpendicular forces for assembly compared to indium, so large arrays can be assembled without excessive bonding forces. Adhesive assembly also compensates better for variations in co-planarity, a major concern with large arrays. Figure 5 shows a portion of a 24 by 44 CdZnTe pixel array stenciled with conductive epoxy for gold stud bump assembly.

Gold stud bump has retained all of the advantages mentioned in earlier tutorials: processing singulated die; allowing raised surface features such as MEMS and RF air bridges; bumping directly to platinum pads for medical/biotech applications; eliminating under-bump metallization (UBM); offering fast turnaround and low equipment cost with no vacuum processes

Gold stud bump flip chip assembly remains a niche compared to pervasive solder bumping. However, increasing capabilities and new applications show that the golden niche is growing, not shrinking. Higher bumping speed, with consequent lower cost, allows the natural advantages of lead-free gold to shine forth.

1. (1) "Stud bumping and die attach for expanded flip chip applications," Vince McTaggart, Lee Levine, and Gene Dunn, Advanced Packaging, September, 2004
2. " Gold stud bump in flip chip applications," Palomar Technologies Application Note  Full Text
3. (3) "Stud bump bonding," Laurie S. Roth and Vince McTaggart, Advanced Packaging, February, 2005.
4. (4) "A comparison of the stud bump performance of 4N and 2N gold wire, " Tok Chee Wei, Chen Hui Hui, Klaus Dittmer, Christopher Breach, and Frank Wulff, Semicon Singapore, 2003.
5. (5) "Challenges of Pb-free packaging of high-power LEDs," Shatil Haque, Serge Rudaz, Frank Wall, Chris Elpedes, Dan Steigerwald, Phil Elizondo, Jerome Bhat, Bob Steward, Dave Collins, Xina Quan, Paul S. Martin, IMAPS International 2004, Long Beach, CA, Nov 14 -18, 2004.
6. (6) "Very high pin count adhesive flip chip assembly using conductive polymer adhesives," James E. Clayton, IMAPS 2003, Boston, MA November 16 -20 2003.

Other tutorials and papers on this site:

1. Tutorial 3.   Stud Bump Flip Chip

2. Tutorial 9.   Thermosonic Flip Chip Assembly

3. Tutorial 10.   Flip Chip Interconnection for Detector Arrays

4. Tutorial 24.   Gold Stud Bump Applications

5. Tutorial 27.   Shaping Gold Ball Bumps

6. Tutorial 29.   Micro-Posts: Tall, Slender, Stud Bumps.

7. Tutorial 33.   Conductive Polymer Assembly of High Pin Count Flip Chip

8. Technology Update, "Stud Bump Flip Chip Assembly of MEMS Motion Sensors"