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George A. Riley, PhD
FlipChips Dot Com

Wafer-level chip scale packaging (WLCSP) is growing rapidly, because it combines the conventional chip-scale package advantages of small size and ease of handling with lower-cost volume production. Hermetic cavity WLCSP also offers mechanical and handling protection, beginning at the wafer level, for devices with fragile surface features, such as RF air bridges. Chip scale packaging (CSP) is becoming common for RFIC packaging, but is also relatively costly. The economies of WLCSP make it an attractive next step for RF packaging. This paper surveys some present and developing technical approaches and some barriers to wafer-level hermetic cavity packaging for RF applications.

Wafer-level chip scale packaging (WLCSP) has been a leading development in high-density packaging in the last half of the 1990’s. WLCSP combines the chip-scale package advantages of small size and ease of handling with an efficient volume production approach based on batch packaging at the wafer level. The essence of WLP is that the packages are formed directly on the wafer, before the wafers are sawn and the die are singulated. It is conventionally referred to as "zero-level packaging," to distinguish it from first-level packaging, which connects the die to a lead frame or separate package.

For standard IC wafers, WLCSP commonly includes adding a dielectric layer, a conductive "redistribution layer," which converts the peripheral IC contact pads to wider spacing in an area array, solder masking and solder bumping of the array, and even coating the bumped array with a pre-applied fluxing underfill for later assembly. These WLCSP die are usually under 10 mm square, with fewer than 100 connections in the area array.

While conventional WLCSP is growing rapidly in consumer applications, several hermetic cavity WLSCP are in development or in production. The earliest of these are for protecting MEMS devices with moving surface elements. The highest volume early application was for MEMS accelerometers used in automotive airbag systems. More recently, non-hermetic cavity WLCSP have been produced in high volume for consumer optical applications, while hermetic cavity WLCSP are being offered for MEMS RF switches The following sections examine a variety of approaches for hermetic cavity WLCSP, as possible candidates for RF packaging.

RF devices have for many years been packaged in metal can, ceramic, and Cerdip cavity packages. Advantages of cavity packaging for RF are that it provides headspace for raised surface features, such as air bridges, protects elements such as RF MEMS switches, and provides a dry air dielectric above the chip surface, normally a design assumption for RF microstrip circuitry.

Chip scale packages are becoming common in RF, particularly for packaging RFICs for cellular telephones and wireless LANS. Lead frame CSPs predominate, in wire-bonded or flip chip versions.¹ Cost pressures could lead to more wafer level chip scale hermetic cavity RF packaging.

Five general technical approaches are considered in this paper: glass frit seal, laminated epoxy seal, metal seal, polymer laser seal, and covalent bond seal. These are discussed roughly in order of age, with advantages, limitations, and examples from several manufacturers.

Among the highest volume hermetic cavity wafer level packages are those used to protect MEMS sensors in automotive airbag systems, as offered by Motorala, Bosch, and others. More recent applications include MEMS RF switches.² The hermetic package provides a controlled atmosphere for MEMS, while protecting the fragile devices during assembly processing.

This wafer level package is created by making a glass frit seal between the MEMS wafer and a cap wafer. The approach is conceptually similar to the long-established use of glass frit as a seal in conventional hermetic ceramic and Cerdip packages. The difference is that now, the glass frit seals the cavity walls between a cap wafer and a device wafer.

The cap wafer is stenciled with a mixture of glass and binder, patterning the walls of each device cavity. Firing the stenciled wafer sinters the stenciled glass onto the cap wafer, providing the cavity walls. In assembly, the glass cap wafer is aligned and thermo-compression bonded to the device wafer, with the glass frit making the hermetic seal. After dicing, the assemblies are mounted and wire bonded into a conventional molded plastic package for board-level interconnection.³ Figure 1 is a cutaway view of a cavity package before encapsulation in the molded plastic.

Fig. 1 Glass frit sealed hermetic cavity WLCSP.

Potential drawbacks of this approach for WLCSP hermetic cavity RF packaging include the thickness of the cap and the large bonding area consumed by the glass frit seal.⁴ A reliable glass frit thermo-compression seal requires a relatively large wall seal footprint on the active wafer, with a resultant penalty in die per wafer. The height of the glass frit cap gives a cap thickness greater than the die, and a total thickness greater than that of alternative hermetic seal methods.

Shellcase Ltd⁵ offers their ShellOp package as a WLCSP solution for image sensors and optical detectors. They provide high-volume wafer level packaging for CMOS and CCD linear and array sensors in commercial applications such as digital cameras. Their patented wafer level package is a glass-silicon-glass sandwich laminated and sealed with epoxy.

The ShellOP approach uses the top glass wafer to provide an optical window. The bottom glass wafer brings out solder bump contacts in a ball-grid array on the bottom side of the die. Figure 2 gives a cross-section diagram.

Fig. 2. ShellOP optical window WLCSP.

Shellcase states that their package may be used with 6" and 8" wafers. They claim multi-million units production for CCD digital cameras, CMOS based sensors, and other commercial applications.

Shellcase has announced a technical initiative to produce a hermetic cavity package for MEMS and other sensors based on the ShellOp approach. However, the seals may still be epoxy, which could limit hermeticity, and raises concerns about potential permeability and outgassing.

MicroCSP Inc⁶, an affiliate of MultiChip Assembly, has developed a hermetic cavity WLCSP for MEMS packaging. The basic MicroCSP package is a laminated glass cap wafer with epoxy sealing. The glass sheet has the same thermal expansion coefficient as silicon. The glass sheet also contains pre-etched vias to match the die bond pads. Thin metal traces are sputtered onto the top of the glass surface, to redistribute the bond pad traces into a solder-bumped ball-grid array.

Figure 3 shows the bridge metalization connecting a pad to the topside trace and a solder ball.

Figure 3 Cross-section diagram of the MicroCSP interconnection.

MicroCSP has recently extended this approach to hermetic cavity packaging for MEMS. The hermetic cavity package uses MicroCSP etch technology to produce cavities, as well as vias, in the glass sheet. The sheet is then laminated to a wafer to produce a cavity package as described above. Following lamination, a V-cut is made in the region of the scribe line, the pad openings are cleaned, and metallization is applied to join the chip to the I/O pads. In this operation, metal is also applied to the V-cuts in the scribe streets. This metallization seals the adhesive bondline between substrate and IC wafer, providing a hermetically-sealed interface after final singulation. Permeability and adhesive outgassing may set limits on the achievable hermeticity and vacuum.

Patents have been issued in the past few years for various metal sealed WLCSP cavity packages. None of these are known to be commercially available at present.

The most recent, a 2002 patent assigned to Agilent, describes a metal-seal stacked-wafer hermetic cavity WLCSP.⁷ The package consists of a device wafer and a cap wafer joined with a gold cold-weld hermetic seal. The seal "gasket" encloses the perimeter of the die, with separate gasket seals for top-side connections for wire-bonding or bumping.

The device wafer is patterned by sputtering or evaporation with gold pads for the perimeter gasket seal and the bond pad gasket seals. The cap wafer uses thick photoresist patterning and electroplating to build up the perimeter gasket and bond pad gaskets walls over a sputtered seed layer. The gasket height and assembly pressure determine the resulting cavity height. After the gaskets are completed, dry etching is used to create high aspect ratio wells partially through the cap.

On completion of the pads, gaskets, and wells, the cap wafer is aligned and sealed to the device wafer by compression and temperatures up to 350 centigrade. The cap wafer is then thinned to expose the connection wells for wire bonding or other connections.

Cookson Electronics has reported favorable preliminary results on a molded polymer hermetic cavity test vehicle developed with Foster Miller, Inc. under a DARPA contract.⁸ The material is liquid crystal polymer (LCP), a thermoplastic with barrier properties an order of magnitude better than epoxy plastic materials.⁹

Discrete molded LCP RF packages are presently offered by at least one supplier.¹⁰ This development explores extending that capability to WLCSP hermetic cavity packages.

The test vehicle has liquid crystal resin molded into a cavity, and sealed to a glass cap. The sealing process takes advantage of the transparent cap to form a laser seal by melting the thermoplastic at the glass interface.

Figure 4 is a diagram of the sealing method. The IR/NIR laser beam passes through the cap with minimal absorption, and is absorbed by the LCP at the glass interface.

Fig. 4 Molded LCP package conceptual diagram, showing laser sealing through the cap.

Preliminary testing of sealed test vehicles showed initial hermeticity passed helium leak testing, per MIL-STD-883D. However, this standard, developed for metal and ceramic packages, may be inappropriate for molded polymer packages with permeability considerations.

Ziptronix¹¹ has introduced a proprietary process for room temperature covalent bonding of silicon wafers and related materials, such as SiO₂ and Si₃N₄. Wafers are planarized, and put through a series of surface conditioning treatments. When the treated surfaces are brought into intimate contact, covalent bonds are created, forming a hermetic seal. Other materials such as GaAs can also be bonded by first coating the seal area with SiO₂.

The process has produced prototype hermetic cavity WLCSP for MEMS, RF, and similar applications. Figure 5 shows a hermetic cavity optical MEMS package, with a glass window. Connections may be made by bumping or wire bonding, external to the hermetic cavity. Prototypes have passed automotive qualification testing. RF device testing shows no degradation from permeation or outgassing. No parts have yet entered volume production.

Fig. 5 Hermetic cavity covalent bond MEMS package, glass window.

Glass frit seal cavity packages have a long manufacturing history for MEMS. The seal is adequate, although it may be fragile in further packaging. However, the large sealing area required reduces die per wafer, raising cost. The thick cap and large seal may not be suitable for larger die.

Laminated cavity packages are in volume production for consumer products. Contact redistribution above or below the die area minimizes size. However, the adhesive seal raises considerations about long-term hermeticity, permeability, and outgassing.

Metal seal packages with hermetic cavities have been patented, but are not known to be in commercial volume production. While the seal appears satisfactory, a planar fan-out may increase cost and complexity.

Molded polymeric cavity packages are in early development. They presumably would be low cost, but the adequacy of hermeticity, permeability, and outgassing must be fully explored.

Covalent bonded cavity packages for MEMS have a true hermetic seal. These packages have not yet reached volume production. Prototypes perform well in qualification tests, and appear suitable for RF cavity packaging. Wafers require careful planarization.

An earlier version of this paper was presented at IMAPS New England 30th Annual Symposium on May 8, 2003.

1. S. Berry & S. Winkler, "Radio Frequency ICs Gaining," Chip Scale Review Vol. 7, March 2003

2. Radant MEMS Inc., www.radantmems.com

3. G. Li & A. A. Tseng, "Low stress packaging of a micromachined accelerometer," IEEE Transactions on Electronics Packaging Manufacturing, Vol 24 No 1, January 2001

4. "SUMICAP Surface micro-machined encapsulation on wafer level," IMEC, January 2000, www.imec.be/SUMICAP

5. ShellCase Ltd., www.shellcase.com

6. MicroCSP Incorporated, www.multichipassy.com/csp.htm

7. Ruby, et. al., United States Patent 6,429,511, issued August 6, 2002.

8. K. Gilleo, "Plastic hermetic packages for MEMS, MOEMS, and optoelectronic devices?" Proceedings APEX 2003, Anaheim, CA March 31, 2003.

9. R. W. Lussignea, "Liquid crystal polymers: new barrier materials for packaging," Packaging Technology, October 1997.

10. RJR Polymers, Inc. "Air cavity packages," www.rjrpolymers.com/air_cavity_packages.asp

11. Ziptronix, Inc. www.ziptronix.com

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