Copper Column Grid Array, A High Performance Lead-Free Alternative

Advancements in area array packaging technology have enabled the miniaturization in electronic products and improvement in product performance. These developments include increased pin counts, finer pitches, larger body sizes, different substrate materials, reduced solder ball diameters, and smaller package pad diameters. In addition, due to application requirements in multiplayer substrate and high density routing, ceramic substrates are often the material of choice for high performance products. These ceramic packages are then typically assembled on high complexity, high layer count, and thicker printed circuit boards; resulting in substantial mismatch in coefficient of thermal expansion (CTE) between these two materials. As a result, second level solder joint reliability of the larger size ceramic packages can be adversely impacted by all of the above factors.

Although the implementation and advancement in Ceramic Column Grid Array (CCGA) technology has addressed some of the second level solder joint reliability issues in the past, regional legislative mandates to ban the use of lead in electronic products in the near future have accelerated efforts to replace leaded electronic parts/assemblies with lead free alternatives. A change to component configuration and solder joint material creates a need to re-evaluate the second level solder joint reliability. The use of copper column on large ceramic substrate, combined with lead-free alloys and assembly, prompting a need to generate data to fill the void in implementing this type of high I/O, large ceramic package in high performance computer system application.

This paper presents the test vehicle, printed circuit assembly, and test results of solder joint reliability Copper Column Grid Array. The effect of the package and board design, reworkability, and solder joint reliability for eutectic PbSn vs. SAC, are discussed.