Electrical Interconnects for 3D Wafer Stacks

3D wafer bonding is becoming increasingly important in packaging of present day electronics and MEMS. By bonding several wafers containing MEMS, microfluidics, and semiconductor IC's, we can create functional wafer-scale Microsystems. A key technology to realizing the potential of 3D wafer stacking consists of the implementation of electrical and fluidic interconnects between wafers. Our previous work demonstrated the formation of fluidic paths between silicon and glass wafers by using Benzocyclobutene (BCB) as the interface material.

In this paper we present design and fabrication results for the formation of electrical interconnects between two bonded wafers via solder reflow. Currently, there are two ways of forming electrical interconnects between two wafers: the first involves bonding the wafers, followed by wafer thinning, DRIE through the stack, and deposition or plating of interconnect metal. The second approach consists of formation of solder bumps before bonding the wafers. A similar approach is used in flip-chip bonding at die level, however, in our case the required thickness of the solder material is less than the thickness of the BCB layer (less than 4 microns) and the diameter has to be less than 30 microns. In addition, the solder reflow temperature must be bounded by the curing and glass transition temperatures of BCB.

Our approach requires the formation of solder bumps by evaporation of Sn-Au alloy. Small solder bump sizes can be achieved by depositing alternating Sn and Au layers in appropriate proportions on top of a base metal pad. Oxide formation affects the reflow of the solder joint, but we inhibit it using a gold top layer. The fabrication process requires a number of established steps such as photolithography, lift-off, e-beam deposition, reflow, alignment and bonding in an EVG wafer bonder. Experimental results of forming the Sn-Au interconnects between BCB bonded Silicon-Pyrex wafers are included.