A study on copper electrodepostion used for via interconnection, for the application of wafer level packaging

Electrodeposition to fill 3D via interconnection, formed for wafer level packaging of IC and RF devices, was performed. Via hole for interconnection was either through-hole type or blind via. When it comes to through-hole type via, it is also applicable for an interposer (organic or silicon one).

Both types of via were filled with plated copper; in copper sulfate based solution containing chloride, suppressor, accelerator, leveler, pulse plating was adopted with reverse current application. By getting optimum condition for plating such as current shape and additive composition, we could get void-free via filling, which possibly leads to good reliability of devices.

Furthermore, additive behavior was investigated using impedance spectroscopy or potential-varying method, in order to disclose the role of additives in copper ion diffusion, and nucleation& growth mechanism.

Especially, the 2-dimensional and 3-dimensional metal phase formation either phase transition (nucleation) or cluster growth will be studied by SEM observation, together with the investigation of crystal growth of the 3D metal bulk phase.

In the case of impedance spectroscopy, the obtained spectra will be analyzed based upon the equivalent circuit comprising constant phase element (CPE), polarization resistance (Rp), and solution resistance (Rs). From the systematic and electrochemical study of via filling, we are going to understand the effect of constricted feature on electrodeposition and to accomplish perfect filling of via with higher aspect ratio.