Assembly Yield Characterization and Void Formation Study on High I/O and Fine-Pitch Flip Chip Interconnects using No-Flow Underfill

The high performance device packaging solutions such as microprocessor, graphics and high speed memory with high I/O density and fine-pitch full area array interconnect applications for over a decade has been achieved with flip chip in package (FCIP) due to its improved electrical, thermal and form factor requirements [1, 2]. Especially, the flip chip assembly process technology using a no-flow underfill material has drawn a lot of attention with its advantages such as simple assembly process steps and high throughput [3]. However, the advanced FCIP assembly using the no-flow underfill has practical challenges in assembly process to achieve high electrical interconnect yield and high reliability performances due to the narrow feasibility of process window. The narrow feasibility of FCIP assembly process inhibits achieving the robust process with existing assembly process methodologies.

Therefore, new methodologies were explored to develop the assembly process of FCIP comprised of high lead solder bumps with eutectic lead-tin cap to achieve robust electrical interconnections using no-flow underfills in the first part of this study. The parameters of assembly process were optimized and finally the high electrical interconnect yield was achieved for high I/O density and fine pitch FCIP assembly.

However, current high yield assembly processes still might not show high reliability performances due to a large amount of voiding in the underfill layer after assembly process. In typical, voids, formed in the underfill between solder bumps or inside the solder bumps during FCIP assembly process using a no-flow underfill, have been considered as one of the critical defects affecting insufficient reliability of FCIP.

In the second part of this study, we have identified the plausible causes of void formation in FCIP using a no-flow underfill through systematic experimentation with different types of test vehicles. Several test vehicles were designed and used to investigate the primary source of underfill void formation with the material and process effects such as underfill flow, material property, and chemical reaction. Among them, the chemical reaction between solder material and flux agents in the underfill during the simultaneous process of solder wetting and underfill curing was identified as one of the most significant factors for void formation in high I/O and fine pitch FCIP using no-flow underfill materials. Furthermore, the identified main cause of void formation was validated using experimental techniques.

In the third part of this study, we have developed theoretical models for the mechanism of underfill void formation based on the bubble nucleation classical theory. The developed models can predict a number of voids, the size of void, and the speed of void growth in FCIP using simulation. In consequence, we have determined the optimal assembly process parameters by the void formation modeling for the high yield and near void-free underfill layer assembly process of FCIP achieving high reliability performance. Indeed, the development of high performance assembly process through experimental process optimization and void formation modeling for the high I/O density and fine-pitch full area array FCIP using no-flow underfill materials has strong impact on electronic packaging and assembly industry.

REFERENCES [1] J. H. Lau, Flip Chip Technologies: McGraw-Hill, 1990. [2] D. Suryanarayana, “Enhancement of Flip-Chip Fatigue Life by Encapsulation,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 14, PP. 218, 1991. [3] Thorpe, R. et al., “Yield analysis and process modeling of low cost, high throughput flip chip assembly based on no-flow underfill materials,” Electronics Packaging Manufacturing, IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 24, Issue 2, Page(s):123 – 135, April 2001