New Encapsulation process for the SiP

By the trend and needs of electronic device, we tried to put many chips in the small foot-printer package. We called it SiP (System in Package) or SoP (System on Package). To achieve high density and high reliability SiP package advanced packaging process technologies are needed. Among them we developed new encapsulation methods.

Until now dispensing methods was regarded as main underfilling methods of flip chip. In the conventional Flip Chip CSP technology, 2 step encapsulation process is needed, which are underfilling and molding. Underfilling and molding processes are conventional encapsulation process. Already a lot of study was done about those process and lots of technology was developed. But those encapsulation technologies aren’t suitable for the 3D Hybrid stack PKG. such as flip chip stack CSP. This PKG has Flip chip bonding and wire boding within one PKG.

If we using conventional encapsulation methods, there are design restrictions such as big spacer for the fillet and dispensing area, CTE mismatch between underfill material and molding material, and complex process step and so on. So in this test we developed new underfilling process, we called it molded underfill. Actually in the past a few company tried to develop this process using one Flip Chip. But we tested three flip chip molded underfill process.

The test vehicle has three 3.5 mm SQ flip chip. one saw filter and several passive component. The package size is 11 mm SQ and the substrate is 4 layer 0.3 mm. We use daisy chin chip and we did electrical test. We used two kinds daisy chain pattern. We studied about process factors to figure out the vital process factors. And we did process condition optimization test. After that we did reliability test to compare the reliability level of molded underfill sample with conventional underfilled and molded sample. in the reliability test MUF sample showed good results.