A 3D-WLCSP Package Technology: Processing and Reliability Characterization

As the move to higher performance and smaller components continues, interest in 3D packaging has moved to the forefront. Current 3D packaging solutions involve a mix of high density circuit boards with stacked ICs using wire bond interconnect. With advances in wafer thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. For emerging applications, further component miniaturization with the added benefit of 3D integration can be realized by Face to Face bonding of fine pitch flip chip components and low profile passives onto a redistribution layer of another silicon component (a wafer level chip scale package – WLCSP). In this manner for example, a flip chip driver could be mounted directly onto a CSP memory component, ASIC, etc..

This paper will present a new low cost 3D Wafer Level Chip Scale Package technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly. Wafer level packaging provides a highly functional platform from which to implement the new package technology incorporating 3D die to wafer integration. Moreover, such a packaging architecture provides a cost effective, rapid time to market alternative to emerging 3D wafer level integration technologies. Further density opportunities are emerge in this Wafer Level 3D packaging space as Through Silicon Vias (TSVs) ramp in production. This 2 part paper will provide an overview of the new 3D-WLCSP technology including both the thin film processing technologies used to customize a device to enable Flip Chip on wafer bonding as well as the assembly challenges associated with and overcome to produce the 3D Face to Face Flip Chip on wafer package..

Development efforts have focused on wafer level processing and high density flip chip placement forming the 3D-WLCSP and the associated challenges that this type of packaging and assembly includes. Key aspects of wafer level processing will be explored including wafer level redistribution, ball drop, wafer thinning, dicing thinned wafers, and flip chip bumping. In this work the flip chip pitch and bump size was varied as well as key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing challenges encountered include flip chip fluxing methods for very fine pitch and small bump sizes, vision recognition of the chip and substrate during assembly, reflowing of the flip chips on a wafer, and underfilling a bumped wafer with chip components in close proximity.

Initial reliability results will be presented which highlight that even though the flip chip is mounted silicon to silicon, the pitch and bump size make it so that the underfill selection has a large impact on the reliability of the assembly. Various aspects of the die to wafer assembly process will be explored including scaling issues with high volume assembly, utilization of low cost underfill approaches such as no flow underfills and wafer applied underfills, and underfill encroachment on the WLCSP balls. Finally, data on 2nd level reliability of the 3D WLCSP will also be presented indicating the reliability of the 3D-WLCSP assemblies mounted on conventional printed circuit boards.