Influence of Dielectric Materials and Via Geometry on the Thermomechanical Behavior of Silicon Through Interconnects

The growing need for increased reliability together with reduced size and weight has demanded the evolution of technology for IC packaging. 3D packaging is an important concept since the vertical stacking of functional layers allows to increase the level of integration and miniaturization by reducing the interconnection length between the different components. Shorter interconnections also result in less parasitic capacitance and inductance and less power consumption. However, an important requirement for the realization of this concept is the realization of wafer through interconnects. Beside the fabrication parameters that need to be taken into account (formation of the vias, deposition of dielectric layers, copper plating, system integration and so on) a good thermomechanical design of the via has to be done in order to guarantee the reliability of the package.

Silicon through via interconnects are subjected to thermal stresses and strains during the assembly process and during subsequent thermal cycling tests. This effect is mainly caused by the high Coefficient of Thermal Expansion (CTE) mismatch between the copper via and silicon wafer and the high stiffness of both materials. The mechanical strains and stresses generated by this CTE mismatch are usually the driving force for the interconnect failure and therefore, have to be minimized. Typical problems are silicon cracking under too high stresses and copper failure under thermal cycling conditions.

Non-linear 2D Finite Element Analysis has been used to simulate the interconnect structure and better understand the relative affects of dielectric materials and via configurations (shape, size) on the induced stress and strain. Realistic 3D effect is included in the model by the axisymmetric assumption.

Simulations with a virtual design of experiment have been performed to identify the sensitivity factors affecting the induced stresses and strains in the copper vias and silicon substrate. Variables include the diameter of the via, thickness of substrate, thickness and properties of the dielectric material (SiO2, BCB or parylene) and mechanical properties of the different selections of material filling on the copper via such as copper, BCB and totally empty.

The objective of these investigations is to establish a qualitative comparison of the reliability for the different types of copper interconnects. The thermomechanical modeling results will be used as a baseline for designing the silicon through vias. The results suggest that using a soft dielectric material like BCB or parylene significantly reduces the risk of silicon crack and via failure.