Effects of Plasma Pretreatment on Flip Chip and CSP Substrate Level Assembly Yield and Reliability

The demand for miniaturized electronics continues to drive advances in system in package modules and high density board level assembly technologies. This in turn further miniaturizes the solder interconnects required for substrate level assembly. The associated micro-miniature solder interconnects are challenging to yield particularly in the low parts per million range required for many applications. Moreover, the thermomechanical reliability and mechanical reliability of the joints decreases rapidly with solder volume decrease typically requiring underfill or underfill like materials be applied to achieve adequate reliability.

A comprehensive study was performed investigating the influence of plasma pretreatment on assembly yield for solder flip chip in package assemblies and chip scale package (CSP) assembly to SIP modules. In addition, a detailed reliability screening was performed on the assemblies to assess the impact of plasma pretreatment on long term reliability of the assemblies. Various plasma pretreatment techniques and two substrate surface finishes (OSP and ENIG) were included in the experimental analysis. Test vehicles consisted of 208 micron pitch solder bumped flip chip assemblies with 88 IO and an 84 IO, 7 mm size, 0.5 mm pitch CSP assemblies.

Flip chip and CSP devices were underfilled with fast flow, snap cure underfill material. Baseline assemblies without plasma pretreatment were tested for comparison. The test vehicles were then subjected to liquid to liquid thermal shock (LLTS) between -40°C and 125°C with 5 minute dwells or AATS between -40°C and 125°C with 10 minute dwells. The components were tested every 100 cycles for continuity in LLTS and every 200 cycles in AATS. The flip chip components were analyzed using scanning acoustic microscopy every 400 cycles and after C-SAM were baked at 80°C for four and a half hours so that moisture from the scanning would not induce delamination or increase delamination growth. Micro-section analysis confirmed the delamination and solder joint cracking as the root causes of failure.

Visual inspection of the plasma treated samples revealed higher more uniform fillet shapes especially in the corners of the components compared with the untreated devices. CSAM analysis indicated no statistically significant difference between the plasma treated and non-plasma treated samples in terms of underfill uniformity and void formation during processing. The flow times for the plasma treated flip chip samples were 12 to 20 percent faster than the non-plasma treated samples. The flow times for the plasma treated CSPs were 55% faster than the flow times for the untreated samples. As for flip chip reliability differences, the plasma treated test vehicles with Au finish had the highest reliability with a 70 improvement over untreated samples. In contrast, the untreated flip chip assemblies with an OSP finish had 78% higher reliability compared with the plasma treated counterpoints. For the CSP components, the reliability of the components were generally the same as the non-Plasma treated samples.