Erik Jung - FhG-IZM
A. Ostmann - TU Berlin
C. Landesberger - FhG-IZM
D. Wojakowski - FhG-IZM
R. Aschenbrenner - FhG-IZM
H. Reichl - TU Berlin

One key to miniaturization developed in the past was the use of unpackaged, bare dice. Eliminating the volume and weight of the package achieved a significant reduction in footprint.

A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC) Here, the use of recent manufacturing methods allows merging the SiP approach with a volumetric integration.

Up to now, most of the systems make use of single- or double-sided populated system carriers. Embedding passive components was a first step forward. A new challenge is to incorporate not only passive components, but also active circuitry (IC´s) along with the necessary thermal management. Ultra thin chips (i.e. silicon die thinned down to less than 50µm total thickness) lend themselves to reaching these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB´s. Micro via technology allows electrical contact from the embedded chip to the outer surfaces of the system circuitry. As an ultimate goal for microsystem integration, the embedding of optical and fluidical system components can also be envisioned.

This paper presents the first attempts to embed thin silicon die into polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable "box-of-bricks" type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA.