Direct Wafer Bonding Technology Applied to 3D Integration On Silicon

In this paper we will review the potentiality of advanced molecular wafer bonding technology for 3D integration on Silicon and its development at CEA-LETI France. The so-called bonding and thinning down method is adapted to specific device requirements. Topics such as planarisation, oxide thickness monitoring, substrate removal, wafer to wafer alignment and ship to wafer will be discussed.

ADVANCED DEVICE: Planar double Gate MOS transistors represents one of the most promising architectures to fulfil the roadmap targets for sub-32nm nodes and offers an ability to naturally integrate strained Si required to enhance the transport properties of ultra-scaled devices. A Planar double gate CMOS transistor with 40 nm metal gate was achieved using wafer bonding as one easy micro- electronic processing step.

3D INTERCONNECTION TECHNOLOGY: interconnection techniques that improve available pin count in 3D structures communication bandwidth and dissipated power are needed. With this concept, wireless capacitive coupling between two CMOS wafers is realised with capacitors generated by molecular wafer bonding of two processed CMOS silicon wafer with precise alignment ; I/O are achieved after bonding by via opening from the upper thinned silicon and through all the active and passive layers of the CMOS. A complete demonstrator was achieved and the results will be presented.

CHIP ON WAFER: Global interconnections are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits are an alternative As a demonstration feasibility a photonic layer was bonded on a CMOS. III-V photodetectors and sources 1.3x1.3 mm dies are then bonded with alignment . An oxide separation of 200 nm between the III-V active layer and the silicon wave guides required for a good coupling was easily obtained on the whole wafer. Alignment using self assembly will be also discussed.