Figure1.gif (24k)
The BCB was etched for ease of viewing.
CLICK on image for 24k GIF
Extended Abstract for 3rd International Advanced Tech Workshop
on Flip Chip Technology
Flip Chip Interconnection using Redistribution Technology
M. Töpper, P. Coskina, K.-F. Becker, O. Ehrmann, H. Reichl
Technical University of Berlin
Fraunhofer Institute for Reliability and Microintegration Berlin, Germany
Gustav Meyer Allee 25
D-13355 Berlin
phone: (+49)-(0)30-314-72845
fax: (+49)-(0)30-314-72835
e-mail: toepper@izm.fhg.de
Since flip chip assembly has become more and more popular for high volume electronic products, the question is whether a chip-scale package (CSP) approach or direct flip chip mounting of a bare die on the board will become the dominant technology of the next years. The wafer-level CSP of Fraunhofer IZM/TU-Berlin is based on a redistribution process which is related to a thin film multilayer process.
The first process step for redistribution is the deposition of a dielectric layer on the wafer to enhance the passivation of the die. Pinholes in an inorganic passivation would give shorts in the rewiring metallization. Polymers are preferred in all thin film applications because of their very low dielectric constant and minimum loss tangents. The polymer layer under the rewiring metallization acts also as a stress buffer layer for the bumping and assembly processes.
In general the polymeric coating must be capable of matching the high performance of other packaging technologies. Using photosensitive polymers requires many fewer processing steps compared to dry-etch materials, thus reducing cost. Table 1 summarizes three different photo-polymers are which are used at the TU-Berlin and the Fraunhofer IZM for thin film applications. The BCB is the only thin film polymer combining excellent electrical properties, high temperature stability, very low water up-take, and a medium curing temperature. Over 270°C the full cure is complete in a few minutes, around 250°C it takes an hour. Photo-BCB is deposited by spin coating.
Table 1: Comparison of commercially available photo-polymers
|
Material |
BCB |
PI |
Epoxy |
|
Supplier |
Dow |
Du Pont |
Ciba |
|
Tradename |
Cyclotene |
Pyralin |
Probelec |
|
Diel. const e (1MHz) |
2.65 |
3.3 |
4.1 |
|
Loss tan d |
0.0008 |
0.002 |
0.02 |
|
CTE [ppm/K] |
52 |
40 |
60 - 70 |
|
Glass transition |
> 350 |
310 |
125 - 130 |
|
Cure Temp. [°C] |
210 - 250 |
350 - 400 |
120 |
|
Water Uptake [%] |
0.2 |
3.0 |
1.4 |
Data from material suppliers and from TU-Berlin / Fraunhofer-IZM
Low electrical resistivity of the rewiring metallization is achieved by electroplating copper. A thin Ti:W layer (200 nm) and 300 nm of Cu are sputtered uniformly over the entire wafer. Ti:W serves as a diffusion barrier for the aluminium pads, which are cleaned before deposition by back-sputtering with Ar. The sputtered Cu layer is used as the plating base. A positive-working photoresist is applied by spin-coating to create the plating mask. 5 µm Cu is electroplated inside the photo-mask.
After metal deposition the photoresist is stripped and the plating base is removed by a combination of wet and dry etching. The rewiring metallization is covered by a solder mask (Photo-BCB). Electroplated Ni with flash Au is used for the under bump metallization (UBM). The reliability of the redistribution layers is comparable to substrates used for MCM-D. Solder balls (eutectic PbSn) are deposited by stencil printing directly on the redistributed wafers. Figure 1 shows part of a redistributed die.
|
Figure1.gif (24k) |
Figure 1. SEM: Bumped redistributed die (BCB/Cu/BCB/Ni/Au/PbSn)
The BCB was etched for ease of viewing. CLICK on image for 24k GIF |
The reliability of the thin film redistribution is as high as for thin film MCM-D substrates. A two-layer Cu-Photo-BCB-Cu test structure (via-chains) was thermally cycled from -65°C to +155 °C with 10 minutes dwell time and 20 minutes ramp time. 1000 cycles were passed without any degradation in the electrical resistivity of the vias. The same test structures passed also 1000 hours at 85 % humidity and 85°C.
The reliability of different approaches to CSP-WLs was compared in a study. The size of the ASIC was 3 mm x 1.9 mm. The CSPs were mounted on an FR4 board. The CSP-WLs fabricated at TU-Berlin / Fraunhofer-IZM had the highest reliability among the different technologies, passing 700 cycles air to air, -40°C / +125°C. Also, no failures were detected after 1000 hours at 85°C / 85 % humidity. In another study which is not finished, underfilled CSP-WLs (die size 1cm x 1cm) passed 1200 cycles air to air -40°C / +125°C.
In summary: For low-count chips a redistributed die is a full CSP which does not need underfill for high reliability. For high-count chips the number of thermal cycles which could be reached without underfill by this simple redistribution technology is limited due to the CTE mismatch between Si and the board. The concept of a stress buffer layer to avoid underfill for larger dice is under development at Fraunhofer IZM. The basic idea is the deposition of an additional polymer layer on the redistribution layer to compensate for the thermal mismatch of die and board and to serve as a base for additional solder balls.