John H. Lau

Express Packaging Systems, Inc.

1137-B San Antonio Road

Palo Alto, CA 94303

(650)919-0300

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Only solder-bumped with pad-redistribution WLCSPs are considered in this study.

There are at least two major reasons why directly attaching the solder bumped flip chip on organic substrates is not popular yet [1, 2]. Because of the thermal expansion mismatch between the silicon chip and the epoxy PCB, underfill encapsulant is usually needed for solder joint reliability. However, due to the underfill operation, the manufacturing cost is increased and the manufacturing throughput is reduced. In addition, the rework of an underfilled flip chip on PCB is very difficult, if it is not impossible.

The other reason is because the pitch and size of the pads on the peripheral-arrayed chips are very small and pose great demands on the supporting PCB. The high-density PCBs with sequential build-up circuits connected through microvias are not commonly available at reasonable cost yet.

Meantime, a new class of packaging called wafer level chip scale package (WLCSP) provides a solution to these problems [1 – 15]. There are many different kinds of WLCSP, for examples, eight different (ChipScale, EPIC, FCT, Fujitsu, Mitsubishi, National Semiconductor, Sandia National Laboratories, and ShellCase) companies’ WLCSP are reported in [2] and six different (EPS/APTOS, Amkor/Anam, Hyundai, FormFactor, Tessera, and Oxford) companies’ WLCSP are reported in [1]. Just like many other new technologies, however, WLCSPs still face many critical issues (only solder-bumped WLCSP will be considered is this study) [1, 2]:

• The infrastructure of WLCSP is not well established
• The standard of WLCSP is not well established
• WLCSP expertise is not commonly available
• Bare wafer is not commonly available
• Bare wafer handling is delicate
• High cost for poor-yield IC wafers
• Wafer bumping is still too costly
• High cost for low wafer-bumping yield, especially for high-cost dies
• Wafer-level redistribution is still too costly
• High cost for low wafer-level redistribution yield, especially for high-cost dies
• Troubles with System Makers if the die shrinks
• Test at speed and burn-in at high temperature on a wafer are difficult
• Single-point touch-up on the wafer is difficult
• PCB assembly of WLCSP is more difficult
• Solder joint reliability is more critical
• Alpha particles produce soft errors by penetrating through the lead-bearing solder on WLCSP
• Impact of lead-free solder regulations on WLCSP
• Who should do the WLCSP? IC Foundries or Bump Houses?
• What are the cost-effective and reliable WLCSPs and for what IC devices?
• How large is the WLCSP market?
• What is the life cycle of WLCSP?

Since 100% perfect wafers cannot be made at high volume today, the true IC chip yield (Y_T) plays the most important role in cost analysis. Also, the physical possible number of undamaged chips (N_c) stepped from a wafer is need for cost analysis, since (Y_TN_c) is the number of truly good die on a wafer. N_c is given by [1, 2, 16]

where

A = xy (2)

and

In Equations (1) – (3), x and y are the dimensions of a rectangular chip (in millimeters, mm) with x no less than y; q is the ratio between x and y; f is the wafer diameter (mm); and A is the area of the chip (in square millimeters, mm²). For example, for a 200 mm wafer with A = 10 x 10 = 100 mm², then N_c ~ 255 chips.

Wafer-level redistribution is the heart of the WLCSPs. The cost of wafer-level redistribution is affected by the true yield (Y_T) of the IC chip, the wafer-level redistribution yield (Y_R), and the good die cost (C_D). The actual wafer-level redistribution cost per wafer (C_R) is:

where C_WR is the wafer-level redistribution cost per wafer (ranging from $50 to $200), Y_R is the wafer-level redistribution yield per wafer, C_D is the good die cost (not the cost of an individual die on the wafer), N_c is given in Equation (1), and Y_T is the true IC chip yield after at-speed/burn-in system tests (or individual die yield). Again, it can be seen that the actual wafer-level redistribution cost per wafer depends not only on the wafer-level redistribution cost per wafer but also on the true IC chip yield per wafer, wafer-level redistribution yield per wafer, and good die cost.

Wafer-level redistribution yield (Y_R) plays a very important role in WLCSP. The wafer-level redistribution yield loss (1-Y_R) could be due to: (1) more process steps; (2) wafer breakage; (3) wafer warping; (4) process defects such as spots of contamination or irregularities on the wafer surface; (5) mask defects such as spot, hole, inclusion, protrusion, break, and bridge; (6) feature-size distortions; (7) pattern mis-registration; (8) lack of resist adhesion; (9) over etch; (10) undercutting; (11) incomplete etch; and (12) wrong materials. It should be noted that wafer-level redistribution are not reworkable. It has to be right the first time, otherwise, someone has to pay for it!

The uses of Equations (1) and (4) are shown in the following examples. If the die size of a 200 mm wafer is 100 mm², true IC chip yield per wafer is 80% (since the importance of Y_T has been shown in [16, 17], only one value of Y_T will be consider in this study), wafer-level redistribution yield per wafer is 90%, wafer-level redistribution cost per wafer is $100, and the die cost is $100 (e.g., microprocessors), then from Equation (1), N_c = 255, and from Equation (4), the actual wafer-level redistribution cost per wafer is $2140. For the same size of wafer if the die cost is $5 (e.g., memory devices), then the actual wafer-level redistribution cost per wafer is $202. It is noted that for both cases, the actual wafer-level redistribution cost per wafer is much higher than the wafer-level redistribution cost (C_WR = $100)!

On the other hand, if the wafer-level redistribution yield is increased from 90% to 99%, then the actual cost for redistributing the microprocessors wafer is reduced from $2140 to $304 and for redistributing the memory wafer is reduced from $202 to $110.2. Thus, wafer-level redistribution yield plays an important role in the cost of wafer-level redistribution and the wafer-level redistribution houses should stride to make Y_R > 99%, especially for expensive good dies

Wafer bumping is the heart of solder-bumped WLCSPs. The cost of wafer bumping is affected by Y_T, C_D, Y_R and the wafer-bumping yield (Y_B). The actual wafer bumping cost per wafer (C_B) is:

where C_WB is the wafer bumping cost per wafer (ranging from $25 to $250), Y_B is the wafer-bumping yield per wafer, Y_R is the wafer-level redistribution yield per wafer, C_D is the good die cost, N_c is given in Equation (1), and Y_T is the true IC chip yield after at-speed/burn-in system tests (or individual die yield). Again, it can be seen that the actual wafer bumping cost per wafer depends not only on the wafer-bumping cost per wafer but also on the true IC chip yield per wafer, wafer-bumping yield per wafer, good die cost, and wafer-level redistribution yield per wafer.

Just like Y_R, wafer bumping yield (Y_B) plays a very important role in wafer bumping. The wafer bumping yield loss (1-Y_B) could be due to: (1) wrong process;, (2) different materials; (3) too tall or short of a bump height; (4) not enough shear strength; (5) un-even shear strength; (6) broken wafers or dies; (7) solder bridging; (8) damaged bumps; (9) missing bumps; and (10) scratch of the wafer.

For the pervious example, if the wafer-bumping yield per wafer is 90% and wafer bumping cost per wafer is $120, then the actual wafer bumping costs per (the microprocessors) wafer are, respectively, $1956 if Y_R = 90% and $2139.6 if Y_R = 99%, and the actual wafer bumping costs per (the memory) wafer are, respectively, $211.8 if Y_R = 90% and $220.98 if Y_R = 99%. Again, it should be noted that the actual wafer-bumping cost per wafer is much higher than the wafer-bumping cost (C_WB = $120).

On the other hand, if the wafer-bumping yield is increased from 90% to 99%, then the actual costs for bumping the microprocessors wafer are, respectively, $303.6 if Y_R = 90% and $321.96 if Y_R = 99%, and the actual costs for bumping the memory wafer are, respectively, $129.18 if Y_R = 90% and $130.1 if Y_R = 99%. Thus, wafer-bumping yield plays an important role in the cost of wafer bumping and the wafer bumping houses should stride to make Y_BY_R > 99%, especially for expensive good dies. If there is no wafer-level redistribution, then there is no wafer redistribution yield loss, i.e., Y_R = 1, then Equation (5) degenerated to that shown in [17].

Based on the foregoing discussions, the total actual cost for solder-bumping and wafer-level redistribution (C_BR) becomes

where

is the sum of wafer-level redistribution cost and wafer-bumping cost (C_WBR) usually charged by the wafer bumping houses.

For our example, the total actual costs of the microprocessor WLCSP are: C_BR = $4096 if Y_R = Y_B = 90%; C_BR = $2443.6 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_BR = $625.96 if Y_R = Y_B = 99%. The total actual costs of the memory WLCSP are: C_BR = $413.8 if Y_R = Y_B = 90%; C_BR = $331.18 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_BR = $240.3 if Y_R = Y_B = 99%. Thus: (1) for both devices, the actual WLCSP costs are higher than the cost ($100 + $120 = $220) charged by the redistribution-bumping houses; (2) this is even more so for the more expensive dies; and (3) Y_R and Y_B play very important roles in WLCSP and Y_RY_B > 99% is a must for WLCSP to be popular.

The hidden cost per wafer is defined as the difference between the actual wafer-bumping and wafer-level redistribution cost, and the wafer-bumping and wafer-level redistribution cost charged by the wafer-bumping houses. From Equation (6), the hidden cost per wafer for solder-bumped WLCSP (C_H) is giving as

or

Equation (9) is shown in Figure 1. It can be seen that, if Y_R = Y_B = 1, then there is no hidden cost (C_H = 0) in solder-bumped WLCSP. That means the wafer-bumping houses are prefect in doing the wafer-level redistribution and wafer bumping. Unfortunately, they cannot and never will, which makes the costs of wafer-level redistribution and wafer bumping so expensive, especially for expensive good dies.

For our example, the hidden costs of the microprocessor WLCSP are: C_H = $3876 if Y_R = Y_B = 90%; C_H = $2223.6 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_H = $405.96 if Y_R = Y_B = 99%. The hidden costs of the memory WLCSP are: C_H = $193.8 if Y_R = Y_B = 90%; C_H = $111.18 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_H = $20.3 if Y_R = Y_B = 99%. Since someone has to pay (or share) for the hidden costs, that is one of the major reasons why solder-bumped WLCSP is not very popular today.

The actual wafer-bumping and wafer-level redistribution cost per good die (C_BR/D) can be determine by

or

For our example, the actual WLCSP costs per the good microprocessor die are: C_BR/D = $20.08 if Y_R = Y_B = 90%; C_BR/D = $11.98 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_BR/D = $3.07 if Y_R = Y_B = 99%. The total actual WLCSP costs per the good memory die are: C_BR/D = $2.03 if Y_R = Y_B = 90%; C_BR/D = $1.62 if Y_R = 90% and Y_B = 99% or Y_R = 99% and Y_B = 90%; and C_BR/D = $1.18 if Y_R = Y_B = 99%. Comparing with the wire bonding technology, these costs are much too high for solder-bumped WLCSP to be competitive, unless it is compensated for by performance, density, and form factor.

For some special applications such as portable electronic products under drop (shock) and vibration kinds of operation conditions, underfills are needed for ensuring the solder joint reliability of WLCSPs. Recently, in order to increase throughput and reduce production time, the research in wafer-level underfill materials and process is very active [10].

For WLCSP, in this process, the underfill is deposited on the entire solder-bumped wafer prior to dicing. During SMT assemblies, the singulated chip is processed as in standard flip chip reflow operations. The key difference is that the pre-underfilled (with build-in flux) solder-bumped chip will be reflowed and cured concurrently between the chip and the organic substrate.

The actual wafer-level underfill cost per wafer (C_U) can be determined by

where C_WU is the wafer-level underfill cost per wafer and Y_U is the wafer-level underfill yield per wafer. The wafer-level underfill yield loss (1 – Y_U) could be due to: (1) more wafer process steps, (2) wrong process, (3) wrong materials, (4) dicing, (5) non-uniformity, (6) not fully cured underfill, (7) damage of solder bumps, (8) breaking the wafer, (9) scratching the wafer, (10) too high a thermal expansion coefficient, and (11) too low a modulus.

The actual wafer-level underfill cost per good die (C_U/D) can be determined by

Thus, from the cost point of view, wafer-level underfill is not a good idea and making solder-bumped WLCSP even more expensive. This can be seen from the first term of the right-hand side of Equation (13) that the underfill cost of the good dies are increased because some of the expensive underfills are waste on the bad dies. Also, the hidden cost of wafer-level underfill per good die is shown in the second term of Equation (13).

It should be pointed out that, in most of the conventional solder-bumped flip chip on low-cost substrate applications, the underfill operation is usually applied to the individual dies after the system test of the assemblies [1, 16]. The reasons are: (1) easy to rework; (2) underfill only the good dies; and (3) no chance to damage the very expensive wafer. Also, from the process point of view, wafer-level underfill will reduce the self-alignment characteristic (which is so unique) of solder-bumped flip chip technology.

If there is no wafer-level pad-redistribution operation, then the actual wafer-level underfill cost per wafer can be determined by

Also, the actual wafer-level underfill cost per good die (C_U/D) without wafer-level pad-redistribution can be determined by

Again, from both cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates.

3. SUMMARY

More than 20 different critical issues of WLCSP have been mentioned. The most important issue (cost) of WLCSP has been analyzed in terms of the true IC chip yield, wafer-level redistribution yield, wafer-bumping yield, wafer-level underfill yield, and die size and cost. Also, useful equations in terms of these parameters have been presented and demonstrated through examples. Some important results are summarized as follows.

• IC chip yield (Y_T) plays the most important role in WLCSP. If Y_T is low for a particular IC device, then it is not cost-effective to house the IC with WLCSP, unless it is compensated for by performance, density, and form factor.
• Wafer-level redistribution yield (Y_R) plays the second most important role in WLCSP. Since this is the first post wafer processing after the IC FAB, the wafer-level redistribution houses should stride to make Y_R > 99% (99.9% is preferred). Otherwise, it will make the subsequent steps very expensive by wasting the material and process on the damage dies.
• Wafer-bumping yield (Y_B) plays the third most important role in WLCSP. The wafer bumping house should strive to make Y_RY_B > 99% (99.9% is preferred) to minimize the hidden cost, since they cannot afford to damage the already redistributed good dies.
• Based on cost and process points of view, wafer-level underfill is not a good idea for solder-bumped flip chip on low-cost substrates.

3. REFERENCES

1. Lau, J. H., Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, New York, NY, 2000.
2. Lau, J. H., and S. W. Lee, Chip Scale Package: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, NY, 1999.
3. Garrou, P., "Wafer Level Chip Scale Packaging (WL-CSP): An Overview", IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000, pp. 198-205.
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7. Mirza, A. R., "One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 676-680.
8. Simon, J., and H. Reichl, "Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S³)", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 81-86.
9. Teutsch, T., T. Oppert, E. Zakel, E. Klusmann, H. Meyer, R. Schulz, and J. Schulze, "Wafer Level CSP using Low Cost Electroless Redistribution Layer", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 107-113.
10. Tong, Q., B. Ma, E. Zhang, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, and C. P. Wong, "Recent Advances on a Wafer-Level Flip Chip Packaging Process", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 101-106.
11. Lau, J. H., C. Chang, and S. W. Lee, "Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 1360-1368.
12. Lau, J. H., S. Pan, and C. Chang, "Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks", Proceedings of IMAPS Microelectronics Conference, September 2000, pp. 857-865.
13. Lau, J. H., T. Chung, S. W. Lee, C. Chang, and C. Chen, "A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP)", Proceedings of SEMI Chip Scale International, September 1999, pp. H 1-8.
14. Jim, K. L., G. Faulkner, D. O’Brien, D. Edwards, and J. H. Lau, "Fabrication of Wafer Level Chip Scale Packaging for Optoelectronic Devices", IEEE Proceedings of Electronic Components & Technology Conference, June 1999, pp. 1145-1147.
15. Lau, J. H., S. W. Lee, and C. Chang, "Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis", to be published in the ASME Transactions, Journal of Electronic Packaging, December 2000.
16. Lau, J. H., Flip Chip Technologies, McGraw-Hill, New York, NY, 1996.
17. Lau, J. H., Cost Analysis: Solder Bumped Flip Chip Versus Wire Bonding", IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, March 2000, pp. 4-11.